A far more elaborate approach is to put many small processors on a chip. Two architectures dominate such designs: single instruction with multiple data (SIMD) and systolic arrays. For SIMD design, each processor executes the same instruction in parallel but on different data. In systolic arrays, a processor does one step of a calculation (always the same step) before passing it's result on to the next processor in a pipelined manner.
SIMD chips include the Inova N64000 and the HNC 100 NAP. The Adaptive Solutions CNAPS systems uses the Inova N64000 to build a SIMD array. The chip contains 64 PE's, with each PE possessing a 9x16 bit integer multiplier, 32-bit accumulator, and 4KBytes of on-chip memory for weight storage[12][11]. All chips execute the same instruction and common control and data buses allow for multiple chips to be combined. The Hecht-Nielson Computers 100 NAP (Neurocomputer Array Processor) contains only 4 PE's but each PE performs true 32-bit floating point arithmetic[14][13]. Weights are stored in off-chip memory and multiple chips can be cascaded.
A systolic array system can be built with the Siemens MA-16[16][15]. The MA-16 provides for fast matrix-matrix operations (mult, sub, or add) of 4x4 matrices with 16-bit elements. The multipler outputs and accumulators have 48-bit precision. Weights are stored off-chip and neuron transfer functions are off-chip via lookup tables. Multiple chips can be cascaded.